The present embodiments relate to electronic circuits and are more particularly directed to an integrated circuit speed capability indicator that may be used for various purposes including performance control and energy efficiency adjustments for an integrated circuit.
Electronic circuits are prevalent in numerous applications and are used in devices in personal, business, and other environments. Demands of the marketplace affect many design aspects of these circuits, including device size, complexity, efficiency, and cost. These aspects are often important in various devices. By way of example, the mobile phone industry is transitioning from devices that are voice oriented to devices that are multimedia oriented, and multimedia applications typically integrate high performance processing cores. As a result, the above-mentioned aspects of size, complexity, efficiency, and cost manifest themselves in various areas, including energy consumption and battery lifetime. These areas are also a concern in various other electronic devices, particularly where energy is a concern such as in other battery-powered applications. Thus, to maintain pace with marketplace demands and supplier goals for these devices, considerations with respect to these factors are of paramount interest. The preferred embodiments are directed to these aspects.
Along with the proliferation of various electronic devices there is also an ongoing effort in the electronics industry to continue to reduce individual component sizes. This latter effort is sometimes described as sub-micron technology, when describing that the gate length of a single transistor on the electronic device is less than one micron. Of course, because a common electronic device is formed with an increasingly large number of transistors, then by reducing the length of each such device, the overall electronic device is reduced in size. Indeed, transistor lengths are now reducing in size toward an area sometimes referred to as ultra-deep sub-micron, corresponding to an ongoing trend to further reduce the size of transistor gate lengths. For example, current technology contemplates transistor gate lengths on the order of 90 nanometers, or even a lesser amount of 65 nanometers, with the expectation that even further size reductions are contemplated.
With the developments described above, the current state of the art uses two known techniques in an effort to control power consumption on certain devices. In a first technique, at certain times of operation, the global power supply voltage and frequency to the device are reduced. In a second technique, the threshold voltage of the transistors on the device is increased, such as by adjusting a back bias to each of the transistors. While each of these approaches has been used in the past to control power consumption, they have certain drawbacks that have been discovered by the present inventors in connection with the preferred embodiments, particularly as transistor geometries continue to decrease. By way of example, it has been observed that the first technique, reduction of the global power supply voltage, may actually cause an increase in total loss of energy per cycle when leakage current is taken into account. More particularly, it is known that for an overall integrated circuit and particularly in contemporary design, at a given time only a portion of the total circuit is operational, while the remaining transistors in the device remain at their respective non-switched states. This is increasingly the case for system-on-chip (“SOC”) devices, where a number of different functional circuits are formed on a single integrated circuit die. On the SOC or a comparable device, the transistors that are temporarily not switched may leak current at a same time that the then-operating transistors are using functionally necessary current to switch state. The present inventors have observed that, for various reasons, the leakage of these non-switched transistors grows ever more considerable relative to the overall device as device geometries decrease. For example, with the reduction in transistor size, the transistor gate oxide, that is, the insulator between the transistor gate and the underlying semiconductor region, is thinner and, thus, current is more likely to leak through this thinner region. As another example, due to the SOC nature of a device as well as the goal of providing high speed switching devices, there is a lesser ability to temporarily isolate the non-switching transistors so as to avoid or reduce the effect of their current leakage. In any event, therefore, when total leakage current is taken into account for the SOC or like device, then lowering the global power supply voltage and as frequency decreases will actually cause more power consumption than if the supply voltage were left alone or as compared to power consumption at higher frequencies. Also in connection with smaller device geometries, the present inventors have observed that increasing transistor threshold voltages by adjusting back bias will moderately reduce power consumption in some instances, yet the amount of reduction may be further improved upon as is achieved with the preferred embodiments.
In view of the above, there is a need to further improve aspects relating to circuit and device performance control and energy efficiency. In one sense, these aspects may be evaluated and potentially responded to by providing an indicator that predicts or provides a guideline to the anticipated operational capability of a larger circuit corresponding to that indicator. The preferred embodiments are directed to such an indicator, and further include an overall system in which the indicator may be included, thereby addressing the numerous aspects discussed above and improving upon the prior art.